Ground bounce in digital VLSI circuits

Ground bounce in digital VLSI circuits

Analysis and Optimization of Ground Bounce in Digital CMOS Circuits

of the ground bounce in digital CMOS circuits. First, an analytical method for calculating of the ground bounce is presented. The proposed method relies on accurate models of the short-channel MOS device and the chip-package interface parasitics. Next the effect of ground bounce on the buffer propagation delay and the optimum taper factor is discussed and a mathematical relationship for total p...

A Digital Metastability Model for VLSI Circuits

PhD Thesis A Digital Metastability Model for VLSI Circuits PhD candidate Thomas Polzer Reviewers Ao. Univ.-Prof. Dipl.-Ing. Dr. techn. Andreas Steininger Prof. Alex Yakovlev, PhD, DSc This thesis develops a digital model for predicting failure rates caused by marginal triggering, so called metastability, of CMOS storage elements. To derive the underlying model, various storage elements are simu...

Skin Effect: A Natural Phenomenon for Minimization of Ground Bounce in VLSI RC Interconnect

As the frequency of operation has attained a range of GHz and signal rise time continues to increase interconnect technology is suffering due to various high frequency effects as well as ground bounce problem. In some recent studies a high frequency effect i.e. skin effect has been modeled and its drawbacks have been discussed. This paper strives to make an impression on the advantage side of m...

Static Simulation of CNTFET-based Digital Circuits

   In this paper we implement a simple DC model for CNTFETs already proposed by us in order to carry out static analysis of basic digital circuits. To verify the validity of the obtained results, they are compared with those of Wong model, resulting in good agreement, but obtaining a lighter ensuring compile and shorter execution time, which are the main character...